`timescale 1ns/1ns
`include "./params.v"
`include "./bmg.v"
module test_bmg;

reg Clock2;
	initial Clock2 = 1; 
	always #2 Clock2 = ~Clock2; 
reg Reset;
reg [`WD_FSM-1:0] ACSSegment; 	
reg [`WD_CODE-1:0] Code; 		
wire [`WD_DIST*2*`N_ACS-1:0] Distance; 	
//reg [`WD_CODE-1:0] CodeRegister;

initial 
begin
	Reset=0;
#10	Reset=1;
#120	Reset=0;
#10	Reset=1;
end

initial
begin
#1	ACSSegment=6'b000000;	//Controled by Clock1
	repeat(128)
	begin
	#2 ACSSegment=ACSSegment+1;
	end
end

initial Code=2'b01;
   initial begin 
      #50 Code = 2'b11;        //2'b11	  			   11 
      #150 Code=2'b10;
end   
initial begin  
#300 $stop;     
end       
BMG bmg(.Reset(Reset),.Clock2(Clock2),.ACSSegment(ACSSegment),.Code(Code),.Distance(Distance));
endmodule

